1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an improvement in a structure of a terminating portion of, e.g., a high-voltage vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) with a high breakdown voltage, which is applied with, e.g., a high frequency voltage.
2. Related Background Art
A structure of a vertical MOSFET is adopted in a power device such as a power MOSFET or IGBT. In particular, the power MOSFET is a key device essential to realization of a high efficiency of a switching power supply which is extensively used in information devices, portable devices or electronic devices. It is effective to increase an operating frequency in order to improve the efficiency of the switching power supply, and performances required in the power MOSFET have been changed from the conventional low-ON resistance orientation to the low-parasitic-capacitance orientation. As to a loss in the power MOSFET, when the operating current is large and the operating frequency is high, the switching loss becomes dominant. A fall time (tf) dominates the switching loss. In order to shorten this fall time and reduce the switching loss, it is important to reduce Qsw which is an electric charge quantity required to charge the parasitic capacitance of the power MOSFET and rg which is a gate internal resistance.
FIG. 21 is a cross-sectional view showing an example of a conventional MOSFET. The MOSFET shown in the drawing is called a planar type MOSFET because of its gate structure. In the conventional planar type MOSFET, polysilicon obtained by doping an impurity with a high concentration is used as a material of its gate electrode 106. Its impurity concentration is approximately 1E19 to 1E20 cm−3, and its resistivity is 400 to 500 μΩ·cm. In order to reduce the parasitic capacitance of the planar type MOSFET, the planar dimension of a gate electrode must be reduced, which is carried out by extremely narrowing a width of the gate polysilicon of a unit MOSFET which is usually called a cell. In this realization of fineness, however, there is a relationship of a so-called trade-off that a reduction in cross section area of a gate electrode increases the gate internal resistance rg.
As a method of overcoming this trade-off, there has been conventionally a salicide (silicide) technology used in a general IC (Integrated Circuit) or the like. In this technology an insulating film called a side wall spacer is provided on a side wall of the gate polysilicon and the resistance of a surface of a gate polysilicon electrode is lowered by forming a metallic compound of silicon and a metal such as titanium (Ti) or cobalt (Co). Using this technology both a reduction in capacitance and a reduction in resistance can be achieved through realization of fineness. Further, a metallic compound can be simultaneously formed on a surface of a source layer while avoiding a short-circuit with an adjacent source layer by using the side wall spacer, thereby advantageously reducing its wiring resistance. This technology is known technology in the field of IC, and by applying this technology to the power MOSFET, both a reduction in capacity and a reduction in resistance of a gate can be achieved, thus it seems that the original problem can be solved. Such an application of the salicide technology to the power MOSFET has been already disclosed in, e.g., Japanese Patent No. 3284992.
Meanwhile, most power devices as typified by the power MOSFET are used in products which deal with a high voltage not less than 30 V. These power devices have a cell portion in which the above-described unit MOSFET is formed as well as a terminating portion which is positioned on an outer periphery of the cell portion and used to maintain a breakdown voltage by relieving an electric field by extending a depletion layer. Since this terminating portion generally tends to have a higher electric field than that in the cell portion, a design thereof requires to take a higher electric field than that in the cell portion into consideration. Further, the reliability of the power device can be assured by existence of the terminating portion which is appropriately designed.
However, Japanese Patent No. 3284992 refers to only the cell portion, and there is no description concerning a design of the terminating portion at all.
For example, in a MOSFET shown in FIG. 21, even if a capacitance is reduced by realizing a fine width of a gate electrode 106, an internal resistance of the gate is not increased since a metal compound of, e.g., a silicide layer 116 on the gate electrode 106 has a low resistance. Comparing specific resistances of polysilicon and a typical material of silicide, e.g., TiSi2, a specific resistance of the metal compound such as silicide is considerably lower by a factor because TiSi2 has a resistance of approximately 15 μΩ·cm, whereas polysilicon has a resistance of approximately 500 μΩ·cm. Therefore, there is an advantage that a reduction in capacitance by realization of fineness can be promoted.
On the other hand, when applying a breakdown voltage, since a distance between channel base layers 108 is short because of realization of fineness of a gate electrode width in an area Rc of the cell portion, depletion of a drift layer 102 in this period occurs with a relatively low voltage. For example, assuming that a concentration of the drift layer 102 is 2E15 cm−3, a concentration of the channel base layer 108 is 2E17 cm−3 and a distance between the channel base layers 108 is 5 μm, depletion occurs with approximately 10 V. A higher voltage is rarely applied in this period, and the voltage is applied to an interface between a bottom of the channel base layer 108 and the drift layer 102. Therefore, a depletion layer extending from the side surface of the channel base layer 108 to the inside is very short.
In the area Rt of the terminating portion, however, as different from the area Rc of the cell portion, since there is no adjacent base layer on the outer side of the base layer 140, a voltage according to its breakdown voltage is necessarily applied. Therefore, a width of the depletion layer extending from the outer side surface of the base layer 140 toward the inside in the terminating portion Rt is longer than a width in the cell portion. In a regular process, there are electric charges on an interface between an oxide film 104 and the drift layer 102, since the base layer 140 in the terminating portion Rt is a P type layer in a case of an N channel type MOSFET in particular, its surface concentration tends to lower. Accordingly, the depletion layer is further apt to extend toward the surface layer of the base layer 140 in the terminating portion. As shown in FIG. 21, when a metallic compound 144 is formed in such a manner that an outer end portion of the metallic compound 144 is positioned on the outer side away from a high-concentration impurity diffused layer 142, there is possibility that the depletion layer extending from the outer side surface of the base layer 140 to its inside may reach the metallic compound 144 such as a silicide layer through the base layer 140. If such a situation occurs, a leak current flows and the breakdown voltage is lowered. The advantage of providing the high-concentration impurity diffused layer 142 cannot be obtained. It is to be noted that a dotted line Pmp shown in FIG. 21 indicates a patterning position of a mask formed in the terminating portion used to form the high-concentration impurity diffused layer 142.
In order to suppress extension of the depletion layer in the terminating portion Rt to the inside of the base layer 140 and maintain the high reliability of the device, as indicated by a broken line circle C in FIG. 22, there is required, e.g., the high-concentration impurity diffused layer 143IM of the same conductivity type as that in the base layer 140, which is formed in the surface layer of the base layer 140 in the terminating portion Rt so as to extend to the outer side away from the metallic compound 144 such as the silicide layer.
Here, since a field plate electrode 202 is formed above the drift layer 102 with the gate oxide film 104 therebetween, patterning must be executed on the further outer side of an outer boundary of a formation plan area of the high-concentration impurity diffused layer 143IM (see the broken line PIMP in FIG. 22), considering a mask matching margin. However, since the high-concentration impurity diffused layer 143IM is usually formed by an ion implantation technique, when patterning of the field plate electrode 202 is carried out at such a position, the gate oxide film 104 is exposed to danger that a dielectric breakdown might occur due to a charge-up at the time of ion implantation.
As described above, in the conventional structure, it is difficult to achieve both stabilization of a breakdown voltage without increasing a process load and a reduction in resistance of the gate electrode.